2.1.1+CPU+Architecture



Memory Data Register: The MDR is used to temporarily store data read from or written to memory. All transfers that happen from the memory to the CPU go through the MDR. Loads data from data bus (reading data) or one of the CPU registers (storing data). Buses: High speed data transfer between the different areas of a computer.
 * ALU: ** The part of the CPU that will process the arithmetic and logical functions in data.
 * Control Unit: ** Will check that the ALU, MAR, and MDR are performing their functions properly. Memory Address Register: Connected to the address bus, this is how the CPU communicates with the address bus. The MAR either holds an instruction address or a data address


 * Components of the Von Neumann Model: **
 * =====**Component**===== || =====**Task**===== ||
 * =====Memory===== || =====Storage of data/programs===== ||
 * =====Processing unit===== || =====Computation/processing of data===== ||
 * =====Input===== || =====Information on the computer===== ||
 * =====Output===== || =====Getting information into the computer===== ||
 * =====Control Unit===== || =====Ensures all parts perform tasks together===== ||

The following two registers enable communication between the memory and processing unit


 * Memory Address Register: MAR **
 * MAR is connected to the address bus
 * MAR is how the CPU communicates with the address bus
 * MAR can hold either an instruction address or a data address


 * Memory Data Register: MDR **
 * MDR is connected to the data bus
 * Data can go in both to and from memory
 * MDR can load its data from:
 * the data bus (for reading data)
 * one of the CPU registers (for storing data)


 * Operation:**

The instruction that the CPU **fetches** from memory is used to determine what the CPU is to do. In the **decode** step, the instruction is broken up into parts that have significance to other portions of the CPU. The way in which the numerical instruction value is interpreted is defined by the CPU's instruction set architecture.

Often, one group of numbers in the instruction, called the op code, indicates which operation to perform. The remaining parts of the number usually provide information required for that instruction, such as operands for an addition operation.

After the fetch and decode steps, the **execute** step is performed. During this step, various portions of the CPU are connected so they can perform the desired operation. If, for instance, an addition operation was requested, the arithmetic logic unit (ALU) will be connected to a set of inputs and a set of outputs.

The final step, **writeback**, simply "writes back" the results of the execute step to some form of memory.



rss url="http://groups.diigo.com/group/comp_sci/rss/tag/2.1.1" link="true" number="10"